# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            narrow_ashr_s64_32_s64amt
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_CONSTANT i64 32
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s64_32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_32
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 32
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s64_33
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_33
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 33
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s64_31
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_31
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 31
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s64_63
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_63
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 63
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s64_64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_64
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 64
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s64_65
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_s64_65
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65
    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 65
    %2:_(s64) = G_ASHR %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name:            narrow_ashr_s32_16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: narrow_ashr_s32_16
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 16
    %2:_(s32) = G_ASHR %0, %1
    $vgpr0 = COPY %2
...

---
name:            narrow_ashr_s32_17
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: narrow_ashr_s32_17
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 17
    %2:_(s32) = G_ASHR %0, %1
    $vgpr0 = COPY %2
...

---
name:            narrow_ashr_v2s32_17
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: narrow_ashr_v2s32_17
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 17
    %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1
    %3:_(<2 x s32>) = G_ASHR %0, %2
    $vgpr0_vgpr1 = COPY %3
...
